1. Field of the Invention The present invention relates to a semiconductor device, and particularly to a semiconductor device able to adjust propagation time of an internal clock signal.
2. Description of Related Art
A DRAM (Dynamic Random Access Memory), which is one of typical semiconductor memory devices, generally has a DLL (Delay Locked Loop) circuit to accurately transfer data at high speed between the DRAM and a memory controller. The DLL circuit generates an internal clock signal that is phase-controlled with respect to an external clock signal supplied from the memory controller. The internal clock signal is used as a timing signal to output read data. Therefore, it is possible to accurately transfer data between the DRAM and the memory controller at high speed.
However, the DLL circuit consumes a relatively large amount of power. In a semiconductor memory device that is required to have low power consumption particularly for use in mobile devices, the DLL circuit may not be provided. In such a semiconductor memory device, the outputting of read data takes place in synchronism with an internal clock signal that is not phase-controlled. Therefore, an output timing of read data is not in synchronism with the external clock signal. More specifically, after a predetermined delay time has passed since a corresponding active edge of the external clock signal, the outputting of read data starts. The delay time is generally referred to as “tAC” (See Japanese Patent Application Laid-Open No. 10-214483).
For the value of delay time tAC, a predetermined allowable range has been set depending on specifications. Therefore, even when there are variations in delay time tAC between a plurality of semiconductor memory devices produced, the semiconductor memory devices can be shipped as non-defective products if the variations are within the allowable range.
However, the problem is that, if the delay time tAC varies, a selection test process after packaging becomes complex. The reason is that, in order to perform the selection tests in parallel for a plurality of semiconductor memory devices that are different in delay time tAC, adjustments need to be made to the output timing of a data strobe signal of each semiconductor memory device. Accordingly, for example, it is desirable that, before the selection tests are conducted, the delay time tAC be measured on a semiconductor wafer; and that, on the basis of the measurement results, the propagation time of the internal clock signal be adjusted in order to reduce variations in delay time tAC. However, it is difficult to use a high-speed tester for a test that is conducted on the semiconductor wafer; a tester whose operating speed is slow is generally used. The problem is that the delay time tAC cannot be measured accurately with such a tester. The problem can arise not only with semiconductor memory devices such as DRAM, but also with all semiconductor devices that output data in synchronization with an internal clock signal that is not phase-controlled.